Question: 74HC163 has two enable input pins which are __ and?

• 1. ENP, ENT
• 2. ENI, ENC
• 3. ENP, ENC
• 4. ENT, ENI

Question: The minimum time for which the input signal has to be maintained at the input of flip-flop is called __ of the flip-flop?

• 1. Set-up time
• 2. Hold time
• 3. Pulse Interval time
• 4. Pulse Stability time (PST)

Question: In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained?

• 1. True
• 2. False
• 3. Both
• 4. None

Question: The divide-by-60 counter in digital clock is implemented by using two cascading counters?

• 1. Mod-6, Mod-10
• 2. Mod-50, Mod-10
• 3. Mod-10, Mod-50
• 4. Mod-50, Mod-6

Question: In a sequential circuit the next state is determined by __ and __?

• 1. State variable, current state
• 2. Current state, flip-flop output
• 3. Current state and external input
• 4. Input and clock signal applied

Question: A 8-bit serial in / parallel out shift register contains the value “8”, __ clock signal(s) will be required to shift the value completely out of the register?

• 1. 1
• 2. 2
• 3. 4
• 4. 8

Question: The minimum time for which the input signal has to be maintained at the input of flip-flop is called __ of the flip-flop.

• 1. Set-up time
• 2. Hold time
• 3. Pulse Interval time
• 4. Pulse Stability time (PST)

Question: The divide-by-60 counter in digital clock is implemented by using two cascading counters:

• 1. Mod-6, Mod-10
• 2. Mod-50, Mod-10
• 3. Mod-10, Mod-50
• 4. Mod-50, Mod-6

Question: In a sequential circuit the next state is determined by __ and __.

• 1. State variable, current state
• 2. Current state, flip-flop output
• 3. Current state and external input
• 4. Input and clock signal applied

Question: A 8-bit serial in / parallel out shift register contains the value “8”, __ clock signal(s) will be required to shift the value completely out of the register.

• 1. 1
• 2. 2
• 3. 4
• 4. 8